The present invention is generally directed to data processors and, more specifically, to a memory circuit capable of storing a current value and previous values of a variable in an address location. The present invention also makes the use of certain non-volatile memories transparent to data processors by making them appear functionally equivalent to standard random access memories.
The power and complexity of microprocessors has increased dramatically in the last twenty years. During that same time period, the relative price of microprocessors has decreased. As a result, most of the population is able to afford a desk top personal computer (PC) that is at least as powerful as some mainframe computers from a decade ago.
However, as more and more functions are either expanded in or added to a microprocessor, the ability of a programmer or engineer to debug problems in a microprocessor or problems in software executed by a microprocessor decreases. This happens, in part, because there are a limited number of pins on a microprocessor that can be used to access and examine the internal registers, buses, interfaces, caches, instruction units, functional units, and other components of a microprocessor. For example, in some processor architectures, read and write operations to an on-chip level one (L1) cache are not directly observable on an external pin of the processor.
A number of techniques may be used to debug a conventional microprocessor and/or to debug software executed by a microprocessor. One technique involves editing source code to include unique print statements associated with particular program branches in order to determine the paths the program took during execution. Another technique involves using a debugger, which causes a program to execute to some break point and then halt. This allows a programmer to modify memory, to analyze certain registers (such as debug registers) that are accessible in the microprocessor, and to change break points, if necessary. Program execution may then be resumed.
These types of techniques are often effective for debugging software, but are frequently of limited use in debugging microprocessors. This is because many debugging techniques are intrusive enough to perturb the normal (and erroneous) operation of the microprocessor, thereby preventing the problem from occurring in the first place.
Certain non-volatile memories, also called flash memories or electrically erasable programmable memories (EEPROM) offer enhanced functionality to the data processing system. However, these memories often require special access instructions or procedures which are not used by conventional volatile memories. For instance, a flash memory must be erased in sectors instead of single memory locations. By contrast, a conventional random access memory can be read and written one storage location at a time. The flash memory must be erased before any new values can be overwritten at an already used location. This makes the use of flash memory impractical at the system level, because in order to change the contents of one location, an entire sector must be erased and rewritten.
Therefore, there is a need in the art for improved techniques for debugging microprocessors. In particular, there is a need for systems and methods for debugging a microprocessor that are minimally intrusive into the normal operation of a highly integrated microprocessor. More particularly, there is a need for systems and methods for accessing and examining selected internal components of a microprocessor without excessively perturbing the normal operation of the microprocessor and without requiring the addition of a large number of external pins.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a memory capable of storing a present value and at least one past value of a variable accessible by a first memory address. In an advantageous embodiment of the present invention, the memory comprises a memory block comprising R rows of memory cells and a row address decoder capable of decoding the first memory address, wherein the row address decoder during a read operation causes data to be retrieved from a row in which data stored to the first memory address was last written and wherein the row address decoder during a write operation causes data to be stored in a next-sequential row following the last-written row.
According to one embodiment of the present invention, the R rows of memory cells are divided into S sub-blocks of rows, each of the S sub-blocks comprising M rows of memory cells, wherein the first memory address accesses a first one of the S sub-blocks of rows.
According to another embodiment of the present invention, the row address decoder comprises a first decoder capable of decoding the first memory address and generating therefrom a sub-block selection signal capable of accessing the first sub-block.
According to still another embodiment of the present invention, the row address decoder comprises a second decoder capable of receiving the sub-block selection signal and generating therefrom a row selection signal capable of accessing one of the next-sequential row and the last-written row in the first sub-block.
According to yet another embodiment of the present invention, the second decoder is further capable of receiving a read/write signal indicating whether a pending memory access operation is a write operation and, if the pending memory access operation is a write operation, generating the row selection signal to allow data to be written to the next-sequential row.
According to a further embodiment of the present invention, the second decoder, if the pending memory access operation is a read operation, generates the row selection signal to allow data to be retrieved from the last-written row.
According to a still further embodiment of the present invention, the memory further comprises a debugging controller coupled to the row address controller and capable of causing the row address controller to sequentially read data from each of the M rows of memory cells in the first sub-block to thereby retrieve the present value and the at least one past value of the variable accessible by the first memory address.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.